Three-Phase Power and Drives
Timer Relays and Practical Timing Diagrams
Compare on-delay, off-delay and timing traces.
You need to understand how “Timer Relays and Practical Timing Diagrams” reached its present form so that older terminology and current practice are not confused.
Read timer-relay waveforms from left to right, distinguish on-delay, off-delay, interval, one-shot and cyclic behavior, and verify every reset and retrigger rule against the selected device.
- Select or check first
- “Off-delay” is not one universal circuit. A signal off-delay can remain powered while its control input changes. A power off-delay must keep its timing function alive after supply removal, commonly with stored energy.
- Controlling assumption
- Circuit state, waveform, source impedance, ratings, temperature and protection topology match the equipment being analysed.
- Top risk
- A logic-correct sequence can still damage the timer. The timing diagram does not prove that a contact can switch the connected load. Motor, solenoid, lamp and capacitive inrush can exceed steady current; DC interruption differs from AC; and suppression components can alter release time.
- Proof
- Check the exact manufacturer data, units and limits, then verify the result by calculation, measurement or a controlled acceptance test.
Start with the basics Optional foundation before “Timer Relays and Practical Timing Diagrams”
Electrical-engineering basics
Electrical behaviour becomes easier to reason about when every voltage has a reference and every current has a complete return path.
- Voltage
- Voltage is potential difference between two points. A voltage statement is incomplete unless both points or its reference are known.
- Current
- Current is charge flow through a path. It does not disappear after a component; in a complete circuit it returns to the source.
- Resistance and impedance
- Resistance opposes steady current. Impedance extends that idea to changing signals and can depend on frequency through capacitance and inductance.
- Power and heat
- Electrical power is the rate of energy transfer. Some becomes useful output and some becomes heat that must stay within component and enclosure limits.
- Rating versus operating point
- A rating is a limit or qualified condition, not a target. The operating point must remain inside all relevant voltage, current, power, temperature and timing limits.
How to use this article: Draw the source, load, reference and return path before calculating. Treat exposed or stored electrical energy as hazardous until isolation is proved.
On this page
A timer relay changes an output according to both an input event and elapsed time. The safest way to understand one is not to memorize a mode name, but to read its timing chart: establish the power state, locate each input edge, measure the specified interval, and then follow the output. Names, terminal functions, reset behavior and retrigger rules vary between manufacturers and even between modes in one product family.
Start with edges, states and a shared time axis
A reliable chart-reading method
- Read every trace on the same horizontal time axis; farther right means later.
- Treat a rising edge as a transition from inactive to active and a falling edge as the reverse. Do not confuse an edge with the duration of the high state.
- Identify whether timing starts from power application, a dedicated start input, a release edge or the removal of supply.
- Follow normally-open and normally-closed contact traces separately when both are shown; they represent complementary contact states, not two independent timers.
- Check what reset does to elapsed time and output, and whether the start input is accepted, ignored or restarts timing while a cycle is active.
On-delay and off-delay place the wait on different edges
Diagram description
The plate assumes a maintained start input and supply present. It is a conceptual comparison, not a universal terminal chart: some off-delay products time after start removal, some after supply loss, and their reset behavior differs.
| Mode | What begins timing | Typical output response | Question to verify |
|---|---|---|---|
| Signal on-delay | Start becomes active | Output changes after the set time if the enabling conditions remain valid | Does removing start reset immediately, retain elapsed time or use another rule? |
| Signal off-delay | Start becomes inactive | Output was active and releases after the set time | Is start retriggerable during the delay? |
| Power-on delay | Timer supply becomes valid | Output changes after startup timing | What minimum off-time is required for a reliable reset? |
| Power-off delay | Timer supply is removed | Stored energy keeps timing briefly before output release | What minimum prior on-time and supported delay range apply? |
Choose the required output waveform before choosing hardware
Diagram description
The one-shot trace produces one fixed-duration output from a start pulse; the interval example turns on with power and later turns off; the cyclic trace alternates while enabled. It does not state whether a pulse can extend, restart or be ignored.
| Required behavior | Common name | Critical detail |
|---|---|---|
| One output pulse of set duration after a trigger | One-shot or monostable | Determine whether additional triggers are ignored, restart the pulse or extend it |
| Output active immediately, then inactive after a set duration | Interval | Confirm whether timing starts from power or a separate signal |
| Repeated alternating output while enabled | Cyclic, repeat-cycle or flicker | Confirm whether the first interval is ON or OFF and whether ON/OFF times are independently set |
| Output active only after an input has persisted | On-delay | Confirm the response when the input disappears before time expires |
| Output retained briefly after an input disappears | Off-delay | Confirm how a new input during the delay affects the remaining time |
Reset is a state transition, not merely a label
Diagram description
This is an intentionally explicit example of one reset-and-retrigger convention. A real device may require a minimum reset pulse, may restart only after a new start edge, or may handle a maintained start differently.
Turn a timing chart into a testable sequence
- Establish initial conditionsRecord supply, start, reset and output states before the first edge. Undefined startup states should not be invented.
- Mark event timesDraw vertical guides through every power, start and reset transition.
- Apply the set intervalMeasure from the exact qualifying edge stated by the data sheet, not from when an operator notices the event.
- Resolve interruptionsUse the manufacturer’s chart for a short input, reset during timing, power interruption and retrigger during an active output.
- Check real constraintsVerify input threshold, minimum pulse width, reset time, contact rating, switching life, supply tolerance and timing accuracy.
Why a timer may not reset after a brief power interruption
Electronic timers contain power supplies, storage components and logic. A short interruption may not discharge them below the internal reset threshold, so the unit can retain state or resume unexpectedly. Manufacturer charts specify minimum power-off or reset-input durations. Design a defined reset path when the sequence depends on returning to a known state.
A timer relay still uses an electrical output stage. Review Mechanical Relays and Their Electrical Ratings for contact limits, then place the timer within the source-to-load chain described in Follow Energy Through an Electrical System.
One-minute questions
Questions to answer before you apply this lesson
What should I select or check first for Timer Relays and Practical Timing Diagrams?
“Off-delay” is not one universal circuit. A signal off-delay can remain powered while its control input changes. A power off-delay must keep its timing function alive after supply removal, commonly with stored energy.
Which assumption can change the conclusion?
Circuit state, waveform, source impedance, ratings, temperature and protection topology match the equipment being analysed.
What can go wrong if I copy the example directly?
A logic-correct sequence can still damage the timer. The timing diagram does not prove that a contact can switch the connected load. Motor, solenoid, lamp and capacitive inrush can exceed steady current; DC interruption differs from AC; and suppression components can alter release time.
How do I verify the result in the real system?
Check the exact manufacturer data, units and limits, then verify the result by calculation, measurement or a controlled acceptance test.
Sources and further reading
- Solid-state Timer H3CROMRON Industrial Automation · 2026-10-13Manufacturer catalogue reviewed for detailed on-delay, off-delay, interval, one-shot, reset, gate and retrigger timing charts and minimum input/reset qualifications.
- Classifications of TimersOMRON Industrial Automation · 2026-10-13Manufacturer guide reviewed for the functional definitions of on-delay, off-delay, interval and flicker operation and the distinction between power-start and signal-start timing.