Motor Control and Timing
NE555 Repeating Timing and Reset
Learn astable charge/discharge cycles and independent reset behavior.
You are applying “NE555 Repeating Timing and Reset” to a real system and need the concept, assumptions and verification boundary to stay clear.
Follow a standard NE555 astable cycle between its trigger and threshold references, calculate high and low intervals, and distinguish reset from control-voltage adjustment.
- Select or check first
- Charge. With the discharge transistor off, current flows from the supply through RA and RB into C. The capacitor voltage rises exponentially toward the supply.
- Controlling assumption
- Sensors, controller logic, actuator limits, timing, fault response and environmental conditions are defined together.
- Top risk
- Do not leave reset or timing inputs undefined. Tie unused inputs to a documented valid state and follow the exact timer variant's data sheet for supply bypassing and CONT decoupling. Breadboard wiring, a noisy supply or a floating RESET lead can look like a mysterious timing fault.
- Proof
- Reach the lower reference. When TRIG observes approximately one-third of VCC, the latch changes back: OUT becomes high, DISCH releases the node and charging begins again.
Start with the basics Optional foundation before “NE555 Repeating Timing and Reset”
Automation-and-control basics
An automatic system measures a condition, decides what it means and commands an actuator while checking whether the expected result actually happened.
- Sensor
- A sensor converts a physical condition into a signal. Its range, uncertainty, response time, environment and failure behaviour matter as much as its nominal output.
- Controller
- A controller reads inputs, applies logic or a control law and issues outputs. Software cannot correct missing measurements, inadequate hardware authority or unsafe architecture.
- Actuator
- An actuator turns a command into physical action, such as motor torque, valve position or switching. Its real limits depend on load, supply, drive and duty.
- Feedback
- Feedback compares measured behaviour with the desired state so error can be corrected. Open-loop command assumes the action occurred; closed-loop control checks it.
- Fault and safe state
- A fault is an abnormal condition that may invalidate control. The safe response must be defined from the hazard and may require independent hardware, not only software.
How to use this article: Trace one complete chain—physical condition, sensor, signal conditioning, controller, drive, actuator and feedback—then ask how each link can fail.
On this page
An NE555 becomes a repeating timer when its output state controls whether an external capacitor charges or discharges. In the standard two-resistor astable connection, the capacitor does not charge from zero to the supply and then empty completely. It repeatedly travels between two internal reference levels—nominally one-third and two-thirds of the supply—while the output changes state at each boundary.
One capacitor voltage creates a repeating state cycle
Diagram description
A schematic and qualitative waveform show the selected TI NE555 astable connection, threshold levels, output states and separate charge and discharge paths.
Steady astable cycle
- ChargeWith the discharge transistor off, current flows from the supply through RA and RB into C. The capacitor voltage rises exponentially toward the supply.
- Reach the upper referenceWhen THRES observes approximately two-thirds of VCC, the internal latch changes state: OUT becomes low and the discharge transistor turns on.
- DischargeThe capacitor now discharges through RB and the DISCH pin toward ground. RA is not in this discharge path.
- Reach the lower referenceWhen TRIG observes approximately one-third of VCC, the latch changes back: OUT becomes high, DISCH releases the node and charging begins again.
The capacitor curve is exponential even when a simplified drawing looks nearly straight. Each interval is finite because the voltage moves between two nonzero fractions of the same supply. For the nominal unforced references, that ratio produces the factor ln(2), approximately 0.693. Component tolerances, leakage, supply decoupling and the timer's specified threshold accuracy determine how closely a real circuit matches the calculation.
High interval for the shown astable
t_H ≈ 0.693 (R_A + R_B) C
Use resistance in ohms and capacitance in farads to obtain seconds. During the high output interval, C charges through both resistors.
- t_H
- output-high duration in seconds
- R_A, R_B
- timing resistances in ohms
- C
- timing capacitance in farads
Low interval and repetition rate
t_L ≈ 0.693 R_B C; f ≈ 1.44 / ((R_A + 2R_B) C)
The period is t_H plus t_L. In this direct positive-resistor circuit, t_H exceeds t_L, so output-high duty cycle is above 50 percent. Different 555 topologies can produce other duty cycles.
- t_L
- output-low duration in seconds
- f
- frequency in hertz
| Assumption | What can change the result |
|---|---|
| NE555 and the shown two-resistor astable | CMOS variants and diode-assisted arrangements may have different limits or paths |
| Nominal one-third and two-thirds references | Control voltage, threshold tolerances and supply disturbance shift them |
| Ideal R and C values | Tolerance, capacitor leakage, dielectric behavior and temperature cause error |
| Settled repeating operation | Power-up can begin from a different capacitor voltage and produce a different first interval |
| Valid operating range | Minimum resistor values, maximum useful frequency and output loading come from the selected data sheet |
Reset and control voltage perform different jobs
Diagram description
The plate distinguishes an active-low reset that forces the output low from a control-voltage input that shifts the threshold and trigger references.
| Input | Immediate effect | Design question |
|---|---|---|
| RESET, active low | Overrides normal timing and forces OUT low; the discharge path is asserted for the selected NE555 | Is the pin driven to valid logic levels at power-up and during faults? |
| CONT | Moves the upper reference; the lower reference is nominally related to it | Are the applied range, source impedance, filtering and bypassing within the selected device data sheet? |
Holding RESET low is not the same as pausing a stopwatch and later resuming at the same point. In the selected circuit it also provides a discharge path, so the capacitor state can change while reset is asserted. After release, the first interval depends on the capacitor voltage, reset timing and supply conditions. If a system needs a precisely defined restart phase, design and verify that behavior explicitly.
Verify the timer as a waveform, not just as a number
Commissioning check
- Confirm the exact part number, supply range and pinout before energizing.
- Calculate nominal t_H, t_L, period and high duty cycle; include R and C tolerance bounds.
- Observe capacitor voltage and OUT with appropriate probes, a common reference and a current-limited low-voltage supply.
- Test power-up, RESET assertion and RESET release instead of measuring only steady operation.
- Check that load current and switching noise do not disturb the timing supply or exceed output ratings.
This timer is one building block inside a larger controller. For the distinction between command and measured response, continue with Open-Loop Commands Versus Real Feedback.
Selection boundary and evidence to keep with the decision
Treat “NE555 Repeating Timing and Reset” as a selection problem, not only a definition. Record the required result, alternatives considered, the controlling assumption and the condition that would change the choice.
Keep evidence proportional to consequence: Reach the lower reference. When TRIG observes approximately one-third of VCC, the latch changes back: OUT becomes high, DISCH releases the node and charging begins again. Revisit the decision when the load, environment, duty, interface, regulation or maintenance plan changes.
One-minute questions
Questions to answer before you apply this lesson
What should I select or check first for NE555 Repeating Timing and Reset?
Charge. With the discharge transistor off, current flows from the supply through RA and RB into C. The capacitor voltage rises exponentially toward the supply.
Which assumption can change the conclusion?
Sensors, controller logic, actuator limits, timing, fault response and environmental conditions are defined together.
What can go wrong if I copy the example directly?
Do not leave reset or timing inputs undefined. Tie unused inputs to a documented valid state and follow the exact timer variant's data sheet for supply bypassing and CONT decoupling. Breadboard wiring, a noisy supply or a floating RESET lead can look like a mysterious timing fault.
How do I verify the result in the real system?
Reach the lower reference. When TRIG observes approximately one-third of VCC, the latch changes back: OUT becomes high, DISCH releases the node and charging begins again.
Sources and further reading
- xx555 Precision Timers data sheet (Rev. K)Texas Instruments · 2026-10-13Primary manufacturer data sheet reviewed for the standard two-resistor astable circuit, nominal threshold levels, timing equations, RESET behavior, CONT function and operating cautions.
- NE555 product information and supportTexas Instruments · 2026-10-13Official product page checked to keep device-family claims conditional on the selected NE555 and to distinguish control-voltage adjustment from reset.